Hardware-Efficient Approximate Dividers for Image Processing in WSN Edge Devices

This paper proposes a hardware-efficient implementation of division, which is useful for image processing in WSN edge devices. For error-resilient applications such as processing, accurate calculations can be unnecessary overhead, and approximate computing that obtains circuit benefits from inaccurate effective. Since there are studies showing sufficient performance with few bit operations, this combinational arithmetic design 16 bits or less. The proposed an restoring division implemented 2-dimensional array 1-bit subtractor cells. main drawback the long “borrow-chain” traverses all rows before final stable quotient result produced, thereby resulting delay excessive power dissipation. two cell designs, named ABSC ADSC, break borrow chain: first vertical direction second horizontal direction, respectively. divider designs compared previous state-of-the-art based on accuracy hardware overhead. have levels close to best achieved by designs. In addition, ADSC had lowest delay, area, characteristics. Finally, both practical showed provide accuracy.